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enpirion EN5312Q fully integrated voltage mode s y nchronous buck pwm dc-dc converter module rev 0.87 januar y , 2006 ro hs co m p lian t preliminary vol t ag e se l e c t da c sw it c h vr ef (+) (-) e rro r am p v se ns e v fb v out vs0 vs 1 vs 2 package bo und r y p- d r iv e n-dri v e uv l o t h e r ma l l i mit c u r r e nt li m i t so ft s t a r t sa w t oot h ge n e r a to r (+ ) (-) pw m co m p v in en ab l e product highlights ? revol u tionary integrated inductor ? tot al foot print as small as 28mm 2 ? onl y two l o w cost mlcc caps requir ed. ? very low solution profile at 1.1mm. ? 4mm x 5mm x1.1mm qfn package ? wide 2.4v to 5.5v input range. ? 1000ma output curr ent. ? less than 1 a st andby current. ? high effici ency, up t o 95%. ? ver y low ri pple volt age; < 10mv ? 3 pin vi d voltage select scheme. ? exter nal divider opti on. ? 5 mh z swi t chin g frequency ? 2% acc u racy ov er line, load, & temp. ? short circuit, uvlo, and ther mal pr otection. ? stabl e wit h up to 100uf out put ca pa cita n c e. product overview the ultra-low-profile en 5312q is targeted to applications where board area and profile are critical. EN5312Q is a complete power conversion solution requiring only two low cost ceramic mlcc caps. inductor, mosfets, pwm, and compensation ar e integrated into a tiny 4mm x 5mm x 1.1mm qfn package. engineered to minimize all source s of converter noise, the EN5312Q eases design and lay o ut constraints. 5 mhz switching frequency and internal type iii compensation provides super i or transient response. with a 1.1 mm profile, the entire layout can occupy as little as 28mm 2 of board area. a 3-pin vid output voltage select scheme provides seven pre-progr ammed output voltages along with an option for extern al resistor divider. output voltage can be programmed on-the-fly to provide fast, dynamic voltage scaling. typical application circui t v in v se ns e v in v s1 v s2 v s0 e n 53 12 q 10 f 4. 7 f v out v ou t gn d en ab l e v fb vo l t a g e se l e ct pf m figure 1. typical applicati o n circuit. applications ? area constrained applications ? set top box/home gateway ? smart phones and pdas. ? voip and video phone s ? personal media player s. ? advanced mobile processors, dsp, io, memory, video, multimedia engines.
rev. 0.87 ? january 2006 en531 2 q 2 absol u te maxi mum r ati ngs maximum electrical r a tings min max vol t a ge s on: v in , v out -0 .3 v 7 . 0 v vol t a ge s on: v sense -0 .3 v v in + 0. 3v vol t a ge s on: v s0 -v s2 -0 .3 v v in + 0. 3v voltage s on: e nabl e -0 .3 v v in + 0. 3v vol t a ge s on: v fb -0 .3 v 1 . 5 v maximum thermal ratings am bient ope ra ting ran g e (i n d u strial rated ) -4 0c +85 c m a x j unct i o n tem p erat ure +12 5 c s t o r ag e t e mp er a t u r e ra ng e - 6 5 c + 1 25 c sol d e r tem p er at ure r a nge m s l3 ( 1 0 sec ) +26 0 c reflow pea k b ody tem p erature +260c electrical characteristics note: v in = 3.6v and t a = -40c to +85c unless otherwis e noted. typ i cal v a lues are at t a = 25c. c in = 4.7uf, c out =10uf parameter sym b ol test co nd i t ions min typ ma x unit s operating input voltage v in 2 . 4 5 . 5 v output voltage v o vs2 vs1 vs0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 v out 3.3 2.5 1.8 1.5 1.25 1.2 0.8 user sel v maximum output current v in = 5v, 0.6v rev. 0.87 ? january 2006 en531 2 q 3 parameter sym b ol test co nd i t ions min typ ma x unit s hysteres is voltage accuracy all parts over line, load and tem p 2 % voltage regulation any given part, over load, line, tem p 1 % soft-star t operation tim e to 90% v out t ss vout = 3.3v 1.6 msec pin d e scri ption v out nc nc nc v out v fb v sense nc nc nc nc v out gn d gn d v in en ab l e vs0 vs1 vs2 1 2 6 5 4 3 10 9 8 7 11 12 13 14 15 16 20 19 18 17 v in e n 5312q v ou t nc nc nc v ou t v fb v se nse nc nc nc nc v ou t gn d gn d v in ena b l e vs 0 vs 1 vs2 1 2 5 4 3 10 9 8 7 11 12 13 14 15 16 20 19 18 17 v in e n 531 2q ag nd 6 figure 3. pin descripti o n, bottom view. figure 2. pin description, top view. v in (pin 1,2): input voltage pin. supplies power to the ic. vin can range from 2.4v to 5.5v. gnd : (pin 3,4): power ground. this pin is internally connected to bottom thermal/ground pad (agnd). i nput and output filter capacito rs should be connected to this pin. good emi design practice dictates that these pins not be connected to other ground connections. the large therm a l pad on the bottom of the package should be the single point of contact to system ground. (refer to section on emi layout consideration for more detail). v out (pin 5,6,7): regulated output voltage. nc (pin 8,9,10,11,12,13,14): these pins should not be electrically connected to each o t her or to any external signal, voltage, or ground. one or m o re of these pins may be connected internally. v sense (pin 15): sense pin for preset output voltages. when using pres et voltages connect this to v load or as close to v loa d as possible to ensure the best regulation. w h e n using external divider, connect this pin to v out. v fb (pin 16): feed back pin for external divider option. w h en using the external divider option (vs0=vs1=vs2= high) connect this pin to the center of the external divider. set the divider such that v fb = 0.6v. vs0,vs1, v s2 (pin 17,18,19): output voltage select. vs0=pin19, vs1=pin18, vs2=pin17. selects one of seven pr eset output voltages or choose external divider by connecting pins to logic high or low. logic low is defined as v lo w 0.4v. logic high is defined as v hig h 1.4v. any level between the s e two value s is inde te rminate. (refer to section on output voltage se le ct for more detail). enable ( p in 20): output enable. enable = logic high, disable = logic low. logic low is defined as v lo w 0.4v. logic high is defined as v high rev. 0.87 ? january 2006 www.enpirion.com
rev. 0.87 ? january 2006 en531 2 q 1.4v. any level between these two values is indete rm inate. agnd (bottom ther m a l/ground pad): system ground for single point grounding. also functions as therm a l pad to rem ove heat from package. connect to surface or p w b internal ground plan e. functional bl ock diagram volt ag e se le c t da c sw it c h vr ef (+) (-) e rror am p v se n s e v fb v out vs 0 vs1 vs2 p a c k ag e b o un dry p- d r i v e n-drive uvl o th erm a l li m i t cu r r e n t li m i t ram p co nt rol so f t sta r t sa w t o o th ge n e r a to r (+ ) (-) pw m co m p v in en ab l e fi gure 4. fu n c ti on al bl ock di agr am . rev. 0.87 ? january 2006 www.enpirion.com 4
rev. 0.87 ? january 2006 en531 2 q typical performance characteristics v i n = 3.6v 60 70 80 90 100 10 0 200 3 0 0 4 0 0 500 600 700 800 9 0 0 1 000 loa d c u r r e n t ( m a ) e f f i ci e n c y ( % ) 3.3v 2.5v 1.8v 1.2v figure 5. efficiency -vs - l o ad, vin = 3.6v. detailed d e scription functi onal ov ervi e w the EN5312Q is a com p lete dcdc converter solution requiring only two low cost mlcc capacitors. mosfet switc hes, p w m controller, gate-drive, com p ens a tion, and inductor are integ r ated into the tin y 4mm x 5mm x 1.1mm package to provide the s m allest footprint possible while m a intaining h i gh ef f i ciency, low quies cent current, and high perform a nce. the converter uses voltage m o de control to provide the simplest im plem entation while also pro v iding ex c e llen t transient response. the de vice operates at a 5 mhz switching f r equency to m a ke pos sible the very sm all components required to enable this unpreceden ted level of integration. enpirion?s proprietary power mosfet technology provides very low switching loss at frequencies of 5 mhz and higher, allowing for the use of very sm al l internal components, and very wide control loop bandwidth. unique m a gnetics allow for high value inductor integrated in to a low profile 1.1mm package. integration of the inductor substantially reduces switching noise and design/layout issues norm a lly associa t ed with switc h-m ode dcdc converters. all of this enables much easier and f a ster integ r ation into v a ri ous applications to m e et dem a nding emi requirem e nts. output voltage is chosen from seve n preset values via a three pin vid voltage select schem e . an external divider option enab les the s e lec tion of a ny voltage in the 3.3v to 0.6v range. this reduces the num b er of com ponents that m u st be qualified and reduces inventory problem s . the vid pins can be toggled on the fly to i m plem ent glitch free dynam i c voltage scaling. protection f eatures include under-voltage lock-out (uvlo), over-cu rren t protection (ocp), short circuit protection, and th erm a l overload protection. integr ate d induc t or for low noi s e design enpirion has introduced the world?s first product f a m ily f eaturing in te grated ind u ctors. the EN5312Q fam ily utilizes a low loss, planar construction inductor. th e use of an internal inductor reduces noise associated with pulsed switching currents that would otherwise be present on the user circuit board. integration m i ni m i zes the path im pedance between the mosfet switches and the inductor electrode, ther eby reducing one of the rev. 0.87 ? january 2006 www.enpirion.com 5
rev. 0.87 ? january 2006 en531 2 q key sources of conducted noise associated w ith switch-m ode dcdc converters. the planar inductor construction orient s the leakage m a gnetic fields in a direction that is orthogonal to those that can couple noise onto signa l traces on the circuit board. further, the package layout is optim ized to reduce the electrical path length for the ac rip p le curren t s th at are the leading sou r ce of radiated em issions from dcdc conve rters. the integrated inductor significantly re duces switching noise effects, reduces parasitic effects that can harm loop stability, and m a kes layout very easy. stable o ver wide range of o p er ating conditions the EN5312Q utilizes an internal type iii com p ensation network and is de s i gne d t o pr ovi de a high degree of stability over a wide range of operating conditions. one of the key features of this device is the ability to add supplem entary capacitance to the output to f u rther im prove transient perform a nce or reduce output voltage ripple. the EN5312Q is stable with up to 100uf of total output capacitance. the very high switching frequency allows for a very wide control loop bandwidth. soft start intern al sof t start c i rcu i ts lim it in-ru sh curren t when the device starts up f r om a power do wn conditio n or when the ?enable? pin is asserted ?high?. digita l contr o l cir c uitry lim its the v out ram p rate to levels that are safe for the power mosfets and the integrated inductor. the soft start ram p rate is nom i nally 2mv/ sec. over curr ent/s h ort circuit pr ote c tion the current lim it function is achieved by sensing the current flowing through a sense p-mosfet which is compared to a reference current. w h en this level is exceeded the p-fet is turned off and the n-fet is turned on, pulling v out low. this condition is m a intained for a period of 1m s a nd then a norm a l sof t start is initiate d. if the over curren t cond ition still pe rsis ts, this c y cle will rep eat in a ?hick-up? m ode. under v o l t age loc k out during initial power up an under voltage lockout circu it will hold-of f the sw itching circuitry until the input voltag e reaches a sufficient level to insure proper operation. if the voltage drops below the uvlo threshold the lockout circuitry will again disable the switching. hysteresis is included to prevent chattering between states. enabl e the enable pin provides a m e ans to shut down the converter or enable norm a l operation. a logic low will dis a ble the con v er ter and cause it to shut down. a logic high will en able the converter into norm a l operation. in shut down mode, the device quiescen t cu rrent will be less than 1 ua. note: this pin m u st not be left floating. thermal shutdown when exces sive power is di ss ipa t ed in th e ch ip, the junction temperature rises. once the junction tem p erature exceeds the therm a l shutdown tem p erature the the r m a l shutdown circu it tu rns of f the converter output voltage thus allowing the device to cool. w h en the junction tem p erature decreases b y 15c , the device will go through the norm a l startup process. rev. 0.87 ? january 2006 www.enpirion.com 6
rev. 0.87 ? january 2006 en531 2 q application information out put voltage sel e ct to provide the highest de g r ee of f l exibility in choosing output voltage, the EN5312Q fa m ily uses a 3 pin vid, or voltage id, voltag e selec t arrangem ent. this allows the designer to choose one of seven preset voltages, o r to use an ex ternal voltage divider. interna lly, the output of the vid multiplex e r sets th e value f o r the voltage ref e r e nce dac, which in turn is connected to the non- inver ting in put of the e rror am plif ier. this allows the use of a single feed back divider with constant loop gain and optim um com p ensation, independent of the output voltage selected. 7 v s 2 v s 1 v s 0 v ou t 0 0 0 3.3v 0 0 1 2.5v 0 1 0 1.8v 0 1 1 1.5v 1 0 0 1.25v 1 0 1 1.2v 1 1 0 0.8v 1 1 1 us er selectabl e table 1 shows the various vs0-vs2 pin logic states and the associated output voltage levels. a logic ?1? indicates a connection to v in or to a ?high? logic vo ltag e level. a logic ?0? ind i cates a connection to ground or to a ?low? logic voltage level. these pins can be either hardw i red to v in or gnd or alternatively can be driven by standard logic levels. logic low is defined as v lo w 0.4v. logic high is defined as v hig h 1.4v. any level between the s e two value s is inde te rminate. exter n al voltage divider as described above, the external voltage divider option is chosen by connecting the vs0, vs1, a nd vs2 pins to vin or logic ?high?. the EN5312Q uses a separate feedback pin, v fb , when using the external divider. vsense m u st be connected to v out as indicated in figure 6. v in v se n s e v in v s1 v s2 v s0 e n 5312 10 f 4 . 7uf v ou t v ou t gn d en abl e ra rb v fb fi gure 6. e x t ernal divider. the output voltag e is selec t ed b y the f o llo wing for m ula: ( ) rb ra out v v + = 1 6 . 0 r a m u st be chosen as 200k ? to m a intain loop gain. then r b is given as: ? ? = 6 . 0 10 2 . 1 5 out b v x r t a bl e 1. v o l t age sel ect set t i n gs. dy namically adjustable output the EN5312Q is designed to allow for dynam i c switching between the predefined vid volt a ge levels, or be tween the p r edef ined o u tput lev e ls and an extern al divide r. the inter - volta ge slew rate is optim ized to preven t excess undershoot or overshoot as the output volta ge levels transition. the slew ra te is iden tic al to the sof t -star t slew rate of 2mv/us. input and output capacitors the input capacitance requirement is 4.7uf. enpirion recommends that a low esr mlcc capacitor be used. the i nput capacitor m u st use a x5r or x7r dielectric form ulation. y5v or equivalent dielectric form ulations loose capacitance rev. 0.87 ? january 2006 www.enpirion.com
rev. 0.87 ? january 2006 en531 2 q with frequency, bias, and tem p erature and are not recomm ended for switch-m ode dc-dc converter input and output filter applications. the output capacitance requirem e nt is a m i nimum of 10uf. the control loop is designed to be stable with up to 100uf of tota l output capacitance. capacitance above the 10uf m i nimum shoul d be added if the transient p e rform a nce is not sufficient using the 10uf. enpirion recomm e nds a low esr mlcc type capacito r b e used. the output capacito r must use a x5r or x7r di electric form ulation. y5v or equivalent dielec tric formulations loose capacitance with frequency, bias, and tem p erature and are not recomm ended for switch-m ode dc-dc converter in put and outp u t filter applications layout consi d erati ons a nd a pplicati on circuits emi considerations for board lay out integrated inductor and plan ar inductor construction go a long way toward reducing m a ny of the sources of emi, both conducted and radiated. however, care m u st still be taken to m i nim i ze potential sources of emi. the package pin-out is carefully engineered to allow for the optim al layout. input, output, and power ground plan es are arrang ed such that the physical size of th e ac current loops can be m i ni m i zed and noisy power ground isolated. 1. single point grounding: to lim it ac current from flowing onto sensitive signal ground planes it is strongly recommended that a single point of contact be used for system ground. the therm a l/ground pad located on the bottom of the package should be used for this comm on grounding point. the pgnd pins, pins 3 and 4, are internally connected to the therm a l/ground pad and so provides for an isolated power ground node for the input and output f ilter capacitors. connect the input and output filter capacitors to these groun d pins as shown in figure 7. do not use these grounds for any other connections. v ou t nc nc nc v ou t v fb v sense nc nc nc nc v ou t gnd gnd v in en abl e vs0 vs1 vs2 1 2 6 5 4 3 10 9 8 7 11 12 13 14 15 16 20 19 18 17 v in ag nd 4. 7 f 10 f v in v out (+ ) (-) (+ ) (- ) figure 7. common point grounding sche matic. 2. pins 9, 11, 12, 13 are connected internally to v drain . keep all s e n s itiv e sign al trac es away from these pins. 3. do not use vias for input and output filter caps. it is very im portant that input and output filter caps be placed on the sam e side of the board as the EN5312Q. at frequencies above 1 mhz, the skin penetration is too shallow for the ac signals to pass properly thr ough a via. the ac currents will instead conduct along the surface of th e planes and potentially couple noise. rev. 0.87 ? january 2006 www.enpirion.com 8
rev. 0.87 ? january 2006 en531 2 q ty pical a pplic ations circuit s example 1 : application utilizing pr eset output voltage, 1.8v . v ou t nc nc nc v out v fb v se nse nc nc nc nc v ou t gn d gn d v in en abl e vs0 vs1 vs2 1 2 6 5 4 3 10 9 8 7 11 12 13 14 15 16 20 19 18 17 v in agnd 4. 7 f 10 f v in v ou t fi gure 8. ap pl i c ati o n ci rcuit with vout = 1.8v. example 2 : application using extern al divider to program v ou t v ou t nc nc nc v ou t v fb v sen s e nc nc nc nc v out gnd gnd v in ena b l e vs 0 vs1 vs2 1 2 6 5 4 3 10 9 8 7 11 12 13 14 15 16 20 19 18 17 v in ag nd 4. 7 f 10 f v in v ou t ra =2 0 0 k rb =1 0 0 k fi gure 9. ap pl i c ati o n dem o ns tra t i n g use o f e x tern al di vi der ou tpu t v o l t age pr ogr a mmi ng ; v out = 1. 8v. rev. 0.87 ? january 2006 www.enpirion.com 9
rev. 0.87 ? january 2006 en531 2 q 10 design consi d erati ons for lead- frame b a sed m odules ex pose d metal on bott om o f pac k a g e lead fram e offers m a ny advantages in therm a l perform a nce, in reduced electrical lead resistance, and in overall foot print. however, they do requi re som e special considerations. in the assembly process lead fram e c onstruction requires that for m echani cal support, som e of the lead-fram e cantilevers be exposed at the point where wire-bond or in ternal passives are attached. this results in several sm all pads being exposed on the bottom of the package. only the agnd/ther mal pad and the perim e ter pads are to be m echanically or electrically connected to the p c board. pwb solder m a sk m u st be used to prevent conn ection to the other pads. figure 11 shows the shape and location of these m e tal pads as well as the m echani cal dim e nsion of the agnd/ther mal pad and the pins. the ?grayed - out? area repres ents th e area that shou ld be protected by solder m a sk on the p w b. therm a l pad. connect to ground plane figure 10. exposed metal and mechanic al dimensions of the package . figure 11 shows the recommended pwb solder m a sk openings. rev. 0.87 ? january 2006 www.enpirion.com
rev. 0.87 ? january 2006 en531 2 q figure 11. p w b sol d er mask openings . n531 2 xxxxx yy w w n531 2 xxxxx yy w w rev. 0.87 ? january 2006 www.enpirion.com 11
rev. 0.87 ? january 2006 en531 2 q contact information enpirion, inc. 685 us route 202/206 s u ite 305 bridgewater, nj 08807 phone: 908-575-7550 fax: 908-575-0775 enpirion reserves the right to make c hanges in circuit d e sign and/ or specifications at any time without notice. information fur nished by enpirion is believed to be accurate and relia ble. e npirion assu mes no responsibil ity for its us e or for infringement of patents or other thir d party right s, whi c h may result from its use. e npirion products are n o t a u thorized for u s e in nuclear control s y stems, as critical components in life suppo rt systems or equipment use d in hazard ous enviro nment without the express written authority from enpirion. rev. 0.87 ? january 2006 www.enpirion.com 12

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